1. Field of the Invention
The present invention relates generally to methods for forming patterned layers when fabricating integrated circuits. More particularly, the present invention relates to plasma etch methods for forming patterned layers when fabricating integrated circuits.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit technology has advanced and integrated circuit device dimensions have decreased, it has become increasingly important within advanced integrated circuits to form patterned layers, such as but not limited to patterned dielectric layers, patterned semiconductor layers and patterned conductor layers, with controlled cross-sectional profiles. As patterned layers become particularly narrow in linewidth and/or pitch, generally less than about 0.25 microns in linewidth and/or pitch, it becomes more difficult with conventional reactive ion etch (RIE) plasma etch methods to form such patterned layers with controlled cross-sectional profiles.
To assist in forming within advanced integrated circuits patterned layers simultaneously possessing: (1) particularly narrow linewidth and/or pitch; and (2) controlled cross-sectional profiles, there has recently been introduced into integrated circuit fabrication the use of high density plasma (HDP) reactive ion etch (RIE) plasma etch methods. High density plasma (HDP) reactive ion etch (RIE) plasma etch methods are typically characterized by plasma densities of greater than about 1E11-1E13 active plasma species per cubic centimeter of plasma. While high density plasma (HDP) reactive ion etch (RIE) plasma etch methods have demonstrated utility within advanced integrated circuit fabrication by assisting in providing patterned layers of particularly narrow linewidth and/or pitch with improved cross-sectional profiles, the use of high density plasma (HDP) reactive ion etch (RIE) plasma etch methods is not entirely without problems. In particular, it has been observed that when high density plasma (HDP) reactive ion etch (RIE) plasma etch methods are employed in etching within advanced integrated circuits layers such as dielectric layers formed of silicon oxide, there is observed a comparatively low etch rate for the dielectric layers and a comparatively high etch selectivity of the high density plasma (HDP) reactive ion etch (RIE) plasma etch method for a photoresist etch mask layer employed in defining the portions of the dielectric layers to be etched. Comparatively low etch rates within high density plasma (HDP) reactive ion etch (RIE) plasma etch methods for layers such as dielectric layers are undesirable since they provide high density plasma (HDP) reactive ion etch (RIE) plasma etch methods which are particularly time consuming. Similarly, comparatively high etch selectivity ratios of high density plasma (HDP) reactive ion etch (RIE) plasma etch methods for photoresist etch mask layers with respect to blanket layers desired to be patterned are undesirable since they may ultimately compromise the improved cross-sectional profile of patterned layers formed employing high density plasma (HDP) reactive ion etch plasma etch methods.
Such a compromise of cross-sectional profile of patterned layers is illustrated by the cross-sectional schematic diagrams of FIG. 1 and FIG. 2. Shown in FIG. 1 is a substrate 10 having formed thereover a blanket layer 12 which is desired to be patterned into a series of patterned layers employing a series of patterned photoresist layers 14a, 14b and 14c formed upon the blanket layer 12. Shown in FIG. 2 is a schematic cross-sectional diagram illustrating the results of further processing of the substrate 10 whose schematic cross-sectional diagram is illustrated in FIG. 1. Shown in FIG. 2 is the results of etching through a high density plasma (HDP) reactive ion etch (RIE) plasma 16 the blanket layer 12 to form the patterned layers 12a, 12b and 12c. When employing the high density plasma (HDP) reactive ion etch (RIE) plasma 16 it is common for the patterned photoresist layers 14a, 14b and 14c to be substantially etched in forming the etched patterned photoresist layers 14a', 14b' and 14c', as illustrated in FIG. 2, thus also eroding the upper edges of the patterned layers 12a, 12b and 12c.
It is thus desirable in the art of advanced integrated circuit fabrication to employ high density plasma (HDP) reactive ion etch (RIE) plasma etch methods which provide superior cross-sectional profile control when forming patterned layers within advanced integrated circuits, while simultaneously providing: (1) enhanced etch rates for those patterned layers; and (2) reduced etch selectivities of photoresist etch mask layers with respect to those patterned layers, that the present invention is generally directed.
Methods through which reactive ion etch (RIE) plasma etch methods may be monitored and/or controlled are known in the art of integrated circuit fabrication. For example, Chen et al., in U.S. Pat. No. 4,493,745 discloses an optical emission spectroscopy (OES) endpoint detection method within which is determined an inflection point at which optical emission intensity of a reactive ion etch (RIE) plasma within a plasma reactor chamber changes when etching a series of integrated circuit layers upon a series of substrates within the plasma reactor chamber. There is then continued the reactive ion etch (RIE) plasma etch reaction for a time period determined by characteristics of the reactive ion etch (RIE) plasma and the series of integrated circuit layers desired to be etched by the plasma. In addition, Savage, in U.S. Pat. No. 5,014,217 discloses an apparatus and method for automatically identifying chemical species within a plasma reactor chamber. The method employs a comparison of the optical emission spectrum (OES) of a plasma within the reactor chamber with a library of predefined optical emission spectra (OES) of various chemical species.
Further, Koshimizu, in U.S. Pat. No. 5,322,590 discloses a method for monitoring and controlling the endpoint when plasma etching silicon oxide layers upon semiconductor substrates. The method employs monitoring the optical emission spectrum (OES) of an active fluorocarbon species employed in etching a silicon oxide layer. Yet further, Birang, in U.S. Pat. No. 5,343,412 discloses a method and apparatus employing optical emission spectroscopy (OES) for determining endpoints of integrated circuit processes, preferably integrated circuit plasma processes, within integrated circuit process chambers. Through the method there is recorded emitted light intensity as a function of time and determined whether the emitted light intensity has a positive slope, a negative slope or a zero slope. Still yet further, Gifford et al., in U.S. Pat. No. 5,347,460 and U.S. Pat. No. 5,546,322 disclose a method and apparatus employing optical emission spectroscopy (OES) for monitoring and controlling a plasma based integrated circuit fabrication process. The method employs a computer to identify various gaseous species in the plasma and subsequently control in a closed loop fashion the plasma through control of appropriate plasma parameters.
Yet still further, Frye et al., in U.S. Pat. No. 5,467,883 discloses an active neural network method and apparatus for controlling wafer attributes in plasma etch processes. The method and apparatus are largely similar with the preceding prior art, with the exception of the addition of an active neural network component. Finally, Hamerich et al., in U.S. Pat. No. 5,395,642 discloses a plasma deposition method for forming within integrated circuits conductor layers having high specific electrical conductivity. The electrical conductivity of the conductor layers is optimized employing an optical emission spectroscopy (OES) method to monitor the energy density of a plasma employed in forming the conductor layers.
Desirable in the art are additional methods through which reactive ion etch (RIE) plasmas employed in forming within integrated circuits patterned layers from blanket layers may be monitored and controlled such that the patterned layers may be formed with desired properties, such as, but not limited to: (1) blanket layer etch rate; and (2) patterned photoresist layer to blanket layer plasma etch selectivity. Particularly desirable are optical emission spectroscopy (OES) methods through which high density plasma (HDP) reactive ion etch (RIE) plasmas employed in forming within integrated circuits patterned layers from blanket layers may be monitored and controlled such that the patterned layers may be formed with desired properties, such as, but not limited to: (1) blanket layer etch rate; and (2) patterned photoresist layer to blanket layer plasma etch selectivity. It is towards these goals that the present invention is specifically directed.